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i.MX8MMini(845s) FlexSPI NOR Flash Boot Question ?

Question asked by Apollo Chang on Mar 5, 2019
Latest reply on Mar 5, 2019 by igorpadykov

We want to try to i.MX8MMini FlexSPI NOR flash Boot

But can't file LUT setting example file in UUU tool ?

And UUU example setting for burn FlexSPI NOR flash.

 

We can see example file (qspi-nor-micron-n25q256a-config , qspi-nor-micron-mt35xu512-config) in i.MX6UL / i.MX6ULL / i.MX7D MFG tool

 

 

i.MX6ULL LUT setting example

 

0            /*dqs_loopback=0 or 1*/
0            /*hold_delay=0 to 3*/
0            /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0            /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/
0            /*device_quad_mode_en=1 to enable sending command to SPI device*/
0            /*device_cmd=command to device for enableing Quad I/O mode*/
0            /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
2000000            /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
3            /*cs_hold_time=0 to 0xF*/
3            /*cs_setup_time=0 to 0xF*/
8000000        /*sflash_A1_size=size in byte(hex)*/
0        /*sflash_A2_size=size in byte(hex)*/
8000000        /*sflash_B1_size=size in byte(hex)*/
0        /*sflash_B2_size=size in byte(hex)*/
0            /*sclk_freq=0 to 6*/
0            /*busy_bit_offset=bit position of device BUSY in device status register*/
2            /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
0            /*sflash_port=0 or 1 (Port B used)*/
1            /*ddr_mode_enable=0 or 1*/
0            /*dqs_enable=0 or 1*/
0            /*parallel_mode_enable=0 or 1*/
0            /*portA_cs1=0 or 1*/
0            /*portB_cs1=0 or 1*/
0            /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0            /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
0            /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
2818043d        /*lut[0] command sequence*/
39040d06        /*lut[1] command sequence*/
2400            /*lut[2] command sequence*/
0            /*lut[3] command sequence*/
0            /*lut[4] command sequence*/
0            /*lut[5] command sequence*/
0            /*lut[6] command sequence*/
0            /*lut[7] command sequence*/
0            /*lut[8] command sequence*/
0            /*lut[9] command sequence*/
0            /*lut[10] command sequence*/

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