# MPC57XX Glitch Filter

Question asked by Christopher Holland on Feb 26, 2019
Latest reply on Feb 27, 2019 by David Tosenovjan

Hi,

Processor Type: MPCX5746C.

Question: Where does the 'n' come from in the following equation: [Filter Period = TCK*MAXCNTx + n*TCK]

I understand TCK: (Prescaled Clock)

TCK = Prescaled Filter Clock Period = T(IRC) x (IFCP + 1)

I understand MAXCNTx: (Number of prescaled clocks for blanking period)

SIUL2 Interrupt Filter Maximum Counter Register

MAXCNTx can be 0 to 15 (for MAXCNT<3 filter will behave as all PASS filter)

15.2.9 SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCRn)
Maximum Interrupt Filter Counter setting
Filter Period = TCK*MAXCNTx + n*TCK
where (n can be 0 to 4)
MAXCNTx can be 0 to 15 (for MAXCNT<3 filter will behave as all PASS filter)
TCK Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value
T(IRC) Basic Filter Clock Period: 62.5 ns (F=16 MHz)
Also note that Filter delay is 2 TCK clock cycles more than Filter period

15.2.10 SIUL2 Interrupt Filter Clock Prescaler Register  (SIUL2_IFCPR)

Interrupt Filter Clock Prescaler setting
Prescaled Filter Clock Period = T(IRC) x (IFCP + 1)
T(IRC) is the internal oscillator period.
IFCP can be 0 to 15

Thank you,