Power up sequence of LS1012AXE7KKB

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Power up sequence of LS1012AXE7KKB

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joseph_lindula
Contributor IV

Hello, I'm a little confused about the Power Up sequence of the LS1012AXE7KKB. On page 30 it describes the power on sequence. For step 1 it doesn't tell the time delta between the power rails. For step 2 it does list a time delta of 95 ms which I understand. Can anyone tell me what is the time delta between the power rails for step 1? Is there a timing diagram that shows the sequence?

Thanks,

Joe

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ufedor
NXP Employee
NXP Employee

The power-up sequence steps are described in the LS1012A Data Sheet, 3.2 Power up sequencing.

General requirements are:

I) duration of step 1 + duration of step 2 <= 75 ms

II) Supply voltages from the same step have no ordering requirement with respect to one another.

Supply voltages from different steps must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.

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ufedor
NXP Employee
NXP Employee

The power-up sequence steps are described in the LS1012A Data Sheet, 3.2 Power up sequencing.

General requirements are:

I) duration of step 1 + duration of step 2 <= 75 ms

II) Supply voltages from the same step have no ordering requirement with respect to one another.

Supply voltages from different steps must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.