LPC11Cxx SPI Master - Slave

[svensavic]

There were lot of questions/answers on this topic. None of them helped resolving my issue though .. 

I have one 11Cxx as a master and another 11Cxx as a slave.

I tapped into SPI lines with logic analyzer and I can clearly see the transfer of the data from Master to slave. With write and "read" requests. I am sending one byte as an address and one byte as a data. And for reading is 1 byte 0x01 and 0xff for data. (expecting response for that byte). "Chip select" is a custom pin (internal pull up mode). It is actually connected to physical SSEL, but running in GPIO func and controlled by software. I can see it on logic analyzer that its pulling low before the clock and data, and pulling high after data transfer. 

I lowered the speed of SPI to get this thing working, so I am using 400kHz config, confirmed with scope.

Slave SSEL is configured as a normal SSEL with pull up mode.

Master is fully happy with that, no interrupts pending there, no busy flags, all fine.

Slave on the other hand is having all sort of problems there. My interrupts on "RX not empty" and "TX not empty" kicked in immediately after initialization of the SPI. And after that SPI get stuck with BSY flag constantly on. No further interrupt happen on slave, even though logic analyzer is showing data.

What should happen when master pulls the select line down and sends the byte of data ?

Will Slave receives that as "RX not empty" interrupt?

How does slave knows it is reading time? Is it just an "agreement", when this byte is received, return data from slave ?

[jeremyzhou]

Hi Sven Savic,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1）What should happen when master pulls the select line down and sends the byte of data?
-- At this point, the slave device should be ready to receive.
2) Will Slave receives that as "RX not empty" interrupt?
-- Actually, I don't find the "RX not empty" interrupt in the Interrupt Mask Set/Clear Register, whether you can clarify it.

3) How does slave know it is reading time? Is it just an "agreement", when this byte is received, return data from the slave?
--It's determined by the SPI protocol.
I've also attached an SPI demo to test both SSP master and slave mode on the LPC11xx MCU, please refer to it for details.

Have a great day.

TIC

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[svensavic]

I had some time to "play" with this. While code for master is working fine, slave is working only if I poll the status bit and react on the status. I can read value back from the master. Writing seems to be more tricky as I am not sure whether I need to read the dummy value from buffer to clear the interrupt status or just throw the value to DR.

This approach is not preferable, as I need to waste cycle time checking whether there is something in the RX buffer. And I can easily hit the timeout if I do some other tasks.

Enabling interrupts just ends with getting overruns. I cant seem to clear the overrun with writing to ICR. My interrupt just gets called again in next cycle. So, basically I get stuck in interrupt deadlock. Thats my original issue explained in the original question.

Why is writing to ICR not clearing overrun interrupt ? Do I need to read from DR even though I got timed out to clear the interrupt ?

[svensavic]

Hi Jeremy,

Will Slave receives that as "RX not empty" interrupt?
-- Actually, I don't find the "RX not empty" interrupt in the Interrupt Mask Set/Clear Register, whether you can clarify it.

I was referring to RXIM interrupt. 

Thanks for the demo, I didnt yet have the time to check it out.