AnsweredAssumed Answered

LPC11Cxx SPI Master - Slave

Question asked by Sven Savic on Feb 25, 2019
Latest reply on Mar 8, 2019 by Sven Savic

There were lot of questions/answers on this topic. None of them helped resolving my issue though .. 

I have one 11Cxx as a master and another 11Cxx as a slave.

I tapped into SPI lines with logic analyzer and I can clearly see the transfer of the data from Master to slave. With write and "read" requests. I am sending one byte as an address and one byte as a data. And for reading is 1 byte 0x01 and 0xff for data. (expecting response for that byte). "Chip select" is a custom pin (internal pull up mode). It is actually connected to physical SSEL, but running in GPIO func and controlled by software. I can see it on logic analyzer that its pulling low before the clock and data, and pulling high after data transfer. 

I lowered the speed of SPI to get this thing working, so I am using 400kHz config, confirmed with scope.

Slave SSEL is configured as a normal SSEL with pull up mode.


Master is fully happy with that, no interrupts pending there, no busy flags, all fine.


Slave on the other hand is having all sort of problems there. My interrupts on "RX not empty" and "TX not empty" kicked in immediately after initialization of the SPI. And after that SPI get stuck with BSY flag constantly on. No further interrupt happen on slave, even though logic analyzer is showing data.

What should happen when master pulls the select line down and sends the byte of data ?

Will Slave receives that as "RX not empty" interrupt?

How does slave knows it is reading time? Is it just an "agreement", when this byte is received, return data from slave ?