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mcf5485 general purpose timer watchdog changing CNt after timer started

Question asked by Raymond Flach on Feb 22, 2019
Latest reply on Feb 26, 2019 by Raymond Flach

Looking at the datasheet MCF5485, for the GMSn register for GPT 0 which I would like to use for the watchdog:


Bits        Name     Description



12           CE          Counter enable. Enables or resets the internal counter during internal timer modes only. CE must be set to enable these modes. If cleared, counter is held in reset.

0 Timer counter held in reset

1 Timer counter enabled

This bit is secondary to the timer mode select bits (TMS). If TMS is1XX, internal timer modes are

enabled. CE can then enable or reset the internal counter without changing the TMS field.

GPIO operation is also available in this mode.



The GCIRn register holds the prescaler and the CNT:


Bits        Name     Description

31–16     PRE       Prescaler. Prescale amount applied to internal counter (in clocks).

Note that in addition to other enable bits and field settings, the PRE field must be written as

non-zero to enable counter operation for all modes except the simple GPIO mode. A prescale of

0x0001 means one clock per count increment.


15–0       CNT       Count value. Sets number of prescaled counts applied to reference events, as follows:

IC—Field has no effect, internal counter starts at 0.

OC—Number of prescaled counts counted before creating output event.

PWM—Number of prescaled counts defining the PWM output period.

Internal Timer—Number of prescaled counts counted before timer (or watchdog) expires.

Reading this register only returns the programmed


My question centers around being able to change the timer period for the watchdog to a different value after initialization and startup of the watchdog.

If I change the GCIRn register CNT value, will it restart the timeout, or will the current value timeout finish first?


Writing a 0 to CE will hold the internal WD timer in reset. So I think if you want to reset the WD timer and set a new CNT value in the GCIRn register and then enable the timer counter with the CE bit, you could.

But maybe there is someone more familiar with the chip that could confirm this? I am looking for the correct sequence to follow.