Is there any relationship between Interrupt Latency and Bus Clk frequency .
That is higher the Bus Clk, lesser is the latency.Something like this.Or it is fixed across the freq?
a) I'm asking you this because latency involves= interrupt identification+ Context saving(Pushing of CPU registers) +Jump to the interrupt vector+time just before first instr of ISR is executed.
b)Is Context saving(Pushing of CPU registers) similar to normal push operation which has definite machine cycles.Or some HW logic sends to the stack on the reception of a trigger ?
From Instruction set I could see some machine cycles allocated for SWI.