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iMX7 CM4 LMEM DDR Caching

Question asked by ALLEN BLAYLOCK on Nov 30, 2018
Latest reply on Feb 20, 2019 by Yuri Muhin
Branched from an earlier discussion



I understand that it is highly recommended to use 0x00000000 - 0x1FFFFFFF for code. Unfortunately to have reasonable performance using DDR memory all data (code and data) must come from the system bus as has been experimentally found here:


My application requires reasonable execution performance (no more than ~2x slower than executing from TCM) and reasonable code space (more than TCM+OCRAM). Therefore I have to use the system bus and run code out of DDR.


When I configured the MPU to have 0x8000_0000 - 0x801f_ffff as catchable and all following memory (0x8020_0000 -> )as uncatchable AND disable instruction access (bit 28 of MPU_RASR register) the M4 core faults with a IACCVIOL. So clearly the cache controller is messing with memory outside of the documented cacheable region. This is unexpected behavior.


What I am looking for with this request is documentation that I can follow and not experience unexpected behavior. What can I do to help facilitate that?