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S12ZVL PLL configuration with CPMUPLL

Question asked by Charudatta Ingale on Feb 20, 2019
Latest reply on Feb 21, 2019 by Diana Batrlova

Hello Team,

 

Let us know appropriate place to configure CPMUPLL in clock configuration.

Currently we are using the given below configuration.

 

CPMUOSC_OSCE=0x01U; /* select external OSC. 10Mhz */


CPMUREFDIV_REFDIV=0x04U; /* select reference divider value */


CPMUREFDIV_REFFRQ=0x00U; /* select REFCLK frequency range Fref <= 2 Mhz */


CPMUSYNR_SYNDIV = 0x0FU; /* set VCO to 64 MHz (bus clock 32 MHz) */


CPMUSYNR_VCOFRQ = 0x01U; /* select VCOCLK frequency range 48Mhz < Fvco <= 64 Mhz */

 

CPMUPLL_FM0 = 0x1U;           /* Enable frequency modulation amplitude 4 % */
CPMUPLL_FM1 = 0x1U;

 

CPMUPOSTDIV_POSTDIV = 0x00U; /* PLL clock = 64 Mhz , divide by 2 (bus clock 32 MHz)*/

while (CPMUIFLG_LOCK == 0U){ /* To solve compiler warning { } added */ }; /* wait till PLL gets locked */

 

Is CPMUPLL configuration place appropriate. ?

 

Let us know if any suggestion to improve our clock configuration.

 

Thanks &  Regards,

Charudatta

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