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S12ZVC SPI Slave without SS ( without CS )

Question asked by Dorde Stojicevic on Feb 20, 2019
Latest reply on Mar 18, 2019 by Edward Karpicz

Hi,

I want to spare a CS (SS) where my S12ZVC acts as a slave.

Configuration with 1 Master and 1 Slave.

 

According to Spec 15.4.3.3 CPHA = 1 Transfer Format it is possible, and I pull my Slave´s SS to ground.

 

"The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.
• Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register,
this data is sent out immediately without a trailing and minimum idle time.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge."

 

Nevertheless, SPIF interrupt is not occuring. The interrupt SS1_Interrupt comes only once after boot and never again.

Why?

 

P.S. Pls see in the spec Figure 15-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1)

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