Purpose of the FlexCAN eDMA Driver

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Purpose of the FlexCAN eDMA Driver

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buettgenbach
Contributor I

Hi,

the Kinetis SDK includes a FlexCAN EDMA driver for RX FIFO. It seems it triggers an interrupt each time a frame is transferred from the head of the FIFO into memory via DMA. I don't see the advantage here? Isn't it the same as just triggering the FlexCAN interrupt on the RX FIFO when a frame is ready????

Is it possible to transfer more then one frame with one DMA request?

Is it possible to transfer multiple frames from a FlexCAN mailbox via eDMA?

Thank you for any response.

Rgds

Markus

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nxf51211
NXP Employee
NXP Employee

Hi Markus,

I'd like to ask which Kinetis are you using and on which driver example are you basing your work. This is for me to know exactly if you could be able to transfer multiple frames, and also how the interrupts work for your case.

Best regards,

Ricardo Delsordo.

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buettgenbach
Contributor I

Hi Ricardo,

thanks for your answer.

we are using the MK64FX512VLQ12 and the SDK 2.5.0 in MCUExpresso IDE. I just realized that the SDK is missing the fsl_flexcan_edma driver which is documented online in the Kinetis SDK 2.0 API Reference Manual. My very first question was based on this implementation. It seems there are no EDMA examples for the flexcan driver in the 2.5.0 SDK?!?! Anyway I'd like to know if it is possible to transfer more than one frame from the FlexCAN FIFO via EDMA without interrupting the processer for each frame and if this is also possible for the mailbox approach.

Rgds

Markus

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nxf51211
NXP Employee
NXP Employee

Hi Markus,

 

Indeed the FlexCAN EDMA is no longer supported with the latest SDK version for the board you’re using; this means that there is no DMA request for the FlexCAN. The reason for this change was due to the fact that the driver had a very specific implementation.

 

Regarding the possibility of transferring more than one frame from the FlexCAN FIFO without interrupting the processor, I’m sorry to tell you that this is not possible. The FlexCAN triggers an interrupt flag every time a frame is transmitted to the FIFO, and the same happens with respect to the mailbox approach (mailbox lock mechanism prevents a new frame to be written into the MB while the CPU is reading it).

 

The module only has the following interrupt sources (none of which could be used to disable the interruption that happens when transferring frames): interrupts due to message buffers and interrupts due to the ORed interrupts from MBs, Bus Off, Error, Wake Up, Tx Warning, and RxWarning.

 

I hope this information can help you.

 

Ricardo Delsordo.

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