MK64FN1M0VLL12 reset causes

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MK64FN1M0VLL12 reset causes

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carmenartamendi
Contributor I

Hi,

I'm working with MK64FN1M0VLL12 microcontroller and I want to know what´s the cause of the reset. 

I forced the reset for different reasons and I always read the same values in RCM_SRS0 and RCM_SRS1 registers. 

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

Can you give more detail of your problem?

Regards,

Jing

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carmenartamendi
Contributor I

Hi Jing,

I want to know the cause of the reset, and when the microcontroller starts working I read RCM_SRS0 and RCM_SRS1 registers.

When a reset is caused by some reprogramation, I read in the RCM_SRS0 register the value of 0x40, which makes sense because I connect the reset pin of the JTAG connector in this pin. 

When the microcontroller is reset because I switch off the power supply, I expect to read the value of 0x80 in RCM_SRS0 register, which indicates the reset has been caused by the power-on detection logic. However, I read in RCM_SRS1 register the value of 0x2, which indicates the reset has been caused by the ARM core indication of a LOCKUP event... I read the same value in RCM_SRS1 register when I force a watchdog reset, and in this case I expect to read the value of 0x2 in RCM_SRS0 register, which indicates the reset has been caused by watchdog reset.

Regards,

Carmen.

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

I tested your problem on my frdm-k64f board. But I didn't see neither of the problem. It is very clear that when power on, SRS0=0x82 and SRS1=0.

You said that LOCKUP bit is 1 and SRS0=0. Yes, The reset value of this SRS1 depends on SRS0=0. Is it means after power on, another reset happen? If yes, I think you may need to check power on sequence. Especially the waveforms of RESET_b and VDD. Voltage of reset pin should not greater than VDD +0.3V during power on.

As to the watchdog bit, can you try the wdog example in SDK?

Regards,

Jing