AnsweredAssumed Answered

iMX7ULP clocks issue

Question asked by Alexandre Bailon on Feb 12, 2019
Latest reply on Feb 12, 2019 by igorpadykov



In order to implement support of interconnect API on iMX7ULP (provides similar features as busfreq),

I would like to scale some clocks.

At runtime, the framework is going to scale nic0, nic1 and ddr clocks, so I must ensure that scaling one of these clocks won't cause any glitches.
The easiest way to do this it to re-parent the clocks which use nic0, nic1, or ddr clock for their peripheral clock.
Basically, I would like to use apll_pfd0, apll_pfd1 or apll_pfd2 as peripheral clock, and apll_pfd3 as source clock of ddr (and so, nic0 and nic1).


But, for some usecases, such as display, default pfd ferquencies are too high, and this can't be used as peripheral clock.
So, I tried to reconfigure the APLL frequency, and the PFDs to have a frequency low enough to be used by peripheral clocks, but since, the display is broken.


After many tests, it looks like that if the APLL frequency is too low (although this respects TRM recommendation),

then the lcdif / dsi doesn't work, although their clocks are exactly the same.

As example, this configuration (default) work:
- PLL frequency: 529200000 Hz (mult: 22, num:1, denom: 20)
- PFD0 (and DDR) frequency: 352800000 Hz (pfd: 27)

- NIC0 (and NIC1) frequency: 176400000 Hz
- LCDIF: 25200000 Hz (640x480@60Hz)

And this one doesn't:

- PLL frequency: 392000000 Hz (mult: 16, num:1, denom: 3)
- PFD0 (and DDR) frequency: 352800000 Hz (pfd: 20)

- NIC0 (and NIC1) frequency: 176400000 Hz
- LCDIF: 25200000 Hz (640x480@60Hz)


In addition of the display that doesn't work, I have also noticed another issue: the rpmsg regulator (used to control the PF1550) stops to work, which breaks many other peripherals such uSDHC.


Could help me to figure out what could be wrong?


For reference, I use the following kernel and bootloader:
git://, rev rel_imx_4.14.78_1.0.0_ga, rev rel_imx_4.14.78_1.0.0_ga


Best Regards,