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CMU_1 & CMU_2 are always giving FLL event occurred irrespective of the value in LFREFR

Question asked by Michael Jihan on Feb 11, 2019
Latest reply on Mar 8, 2019 by Dan Teodorescu

Hi all,

 

   I am trying to configure Clock Monitoring Unit (CMU) for MPC5777C. I have configured CMU_0 to CMU_7.

all my CMU's are working as expected, except for CMU_1 which is monitoring core_clk running at 264MHz

and CMU_2 which is monitoring plat_clk running at 132MHz.

 

These two are always generating FLL event occurred for CMU_LFREFR as low as 0x1. How do i solve this issue?

 

I am calculating the LFREFR value (for core_CLK) as (264000000U * 64.0) / (f_IRCOSC * 1.05)  where f_IRCOSC is obtained by frequency metering and comes around 15.93 MHz. i am then setting the value to the register and enabling CME. following which i am clearing CMU_ISR register to reset any flags that were set before enabling. 

 

I have also tried giving a huge delay after and before Enabling CME but had similar results.

 

 

DEBUGGER O/P

CMU_1_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_1_FDR 00000000 FD 000000
CMU_1_HFREFR 0000045B HFREF 045B
CMU_1_LFREFR 000003F1 LFREF 03F1
CMU_1_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_1_MDR 00000000 MD 000000

 

CMU_2
CMU_2_CSR 00000001 SFM 00: Frequency measurement is completed or not yet started
CKSEL1 00: CLKMT0_RMN is selected
RCDIV 00: CLKMT0_RMN?/?1 (No division)
CME 01: CLKMN1 monitor is enabled
CMU_2_FDR 00000000 FD 000000
CMU_2_HFREFR 0000022D HFREF 022D
CMU_2_LFREFR 000001F8 LFREF 01F8
CMU_2_ISR 00000002 FLCI 00: No FLC event
FHHI 00: No FHH event
FLLI 01: FLL event occurred
OLRI 00: No OLR event
CMU_2_MDR 00000000 MD 000000

 

Thanks

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