Single Ended or Differential Clock on T1024

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Single Ended or Differential Clock on T1024

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abhishekborana
Contributor II

Hii...   In my T1024 Custom Board,  I have connected only single ended SYSCLK as 100Mhz. I have not connected differential clock on DIFF_SYSCLK / DIFF_SYSCLK# .....  There is a field in RCW : Bits 186-187 DDR_REFCLK_SEL.

which define source of  DDR PLL to select as single ended or differential.  There is also defined by cfg_eng_use0.

Does cfg_eng_use0 has higher priority over RCW loaded from Flash ?

Also let me know if I will not able to use any feature of T1024 processor by not giving a provision of differential clock on PCB.   Is there any disadvantage ?

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ufedor
NXP Employee
NXP Employee

> Does cfg_eng_use0 has higher priority over RCW loaded from Flash ?

The cfg_eng_use0 setting is required to select correct SYSCLK source for boot operation - i.e. before and during the RCW acquisition. Of cource the cfg_eng_use0 setting should match the RCW[186-187] value.

> Also let me know if I will not able to use any feature of T1024 processor by not giving

> a provision of differential clock on PCB.   Is there any disadvantage ?

No disadvantage.

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