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Is this an e200z6 embedded Floating-Point APU implementation issue?

Question asked by Michael Hul on Feb 6, 2019
Latest reply on Feb 8, 2019 by David Tosenovjan

In section 3.6.4.1 "Options for Embedded Floating-Point APU Implementations" of the e200z6 PowerPC core manual, the following option implementation is stated:

 

Option:  If an operand for a calculation or conversion is denormalized, the implementation may choose to use a same-signed zero value in place of the denormalized operand.

e200z6 Implementation: The e200z6 uses a same-signed zero value in place of the denormalized operand.

 

However, this appears to not be true.

 

For example, given the following two single-precision float variables with values as shown:

float a = 1.98e-43; //(0x0000008D)

float b = -125; //(0xC2FA0000)

 

Any equation or comparison between these two operands (ex. "a + b" or "a > b") results in an SPE Data Exception due to inexact result (FINXS and FINVS bits set in the SPEFSCR). Based on the implementation described in the manual above, I would have expected that the FPU would use the "same-signed zero value" in place of the denormalized value stored in variable 'a' and not throw an exception. Have I misunderstood the manual, or is this actually an issue in the floating-point APU of the e200z6 core?

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