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Vybrid VF50 BootROM fuse bank CRC checking

Question asked by Jan Simak on Feb 5, 2019
Latest reply on Feb 8, 2019 by Edward Karpicz

Hi,

we use SoC module Colibry VF50 produced by Toradex - module contains VF50 MPU, a NAND flash and a DDR3 ram.

With original configuration from Toradex the MPU works properly. Original configuration uses ext.oscilator ( i.e. OSC_BYPASS fuse is not blown ).

Problem is that when an ext.oscilator clock failure occurs ( just temporary failure ) then MPU freeze forever ( testing can be done in u-boot ). So we configured the MPU to reset it when FOSC is less than 40MHz - register SRC_SICR[CMU_OLR]. It works as expected, but we have another issue.

When MPU resets and ext.oscilator is not working properly BootRom enters into safe fail mode - serial download ( ref.manual 7.5.4.3 Clocks at Boot Time ).

We intended to avoid this with blowing of OSC_BYPASS fuse. After the OSC_BYPASS fuse is blown, the MPU after reset / power up always enters to serial download mode immediately and we have no idea why.

Could problem be that we modified only OSC_BYPASS fuse and didn't modify CRC for given fuse bank? Does the VF50 BootROM do checking of the fuse bank CRC?

When BootROM decides to enter fail safe mode ( serial download ) - is the failure reason stored as an error code in a register - to have possibility to get it and analyze it?

 

Thank you.

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