I see a very similar issue on i.MX6SoloX CPU. The EIM bus is configured into 32-bit non-multiplexed asynchronous mode - ARD=SRD=0.
When I program registers according to the manual I'm getting around 160ns between successive assertions of /CS line.
I.e. setting RCSA/RCSN to zero, RADVA/RADVN, OEA/OEN and the functionally identical registers for write cycle. With RWSC/WWSC set to 10 I can see a correct read/write cycle. CSREC (CS cooldown) is also zero.
Under U-Boot a delay between successive reads or read/writes is ~160ns.
Under Linux (i.e. with MMU) it growth to 250ns or so.
The read or write cycle is simply a set of consecutive LDR commands from a bus address to a register so I can exclude cache/memory access from the timing
I also tried changing aforementioned parameters to one with a correct extension of the cycle.
The only time I was able to get CS back to back is when I programmed RWSC to be less than OEA+OEN or RCSA+RCSN, for example RWSC=5 while OEA=OEN=RCSA=RCSN=3 which is obviously in violation of the timing diagrams provided.