It is not clear to me how the SCU boots the general purpose M4.
My understanding of Cortex M4 processors is that upon PoR, the the stack pointer and reset handler addresses are fetched at the physical address 0x00000000 (assuming VTOR is always set to 0x00000000 upon PoR). I cannot find anything in Revision A of the reference manual that says how the physical address 0x00000000 from the perspective of the general purpose M4 translates to a physical address from the perspective of the system. Revision D of the reference manual also seems to be lacking this information.
I see that the SCU can be instructed to place the image for the general purpose M4 in either the TCM of the general purpose M4, the OCRAM, or lower part of DRAM. However, from the perspective of the general purpose M4, none of these locations map to the physical address 0x00000000. How does the SCU inform the general purpose M4 to find the stack pointer and reset handler addresses at a physical address other than 0x00000000 upon PoR?