IMX8QXP General Purpose M4 Boot Process

[paul_katarzis]

It is not clear to me how the SCU boots the general purpose M4.

My understanding of Cortex M4 processors is that upon PoR, the the stack pointer and reset handler addresses are fetched at the physical address 0x00000000 (assuming VTOR is always set to 0x00000000 upon PoR). I cannot find anything in Revision A of the reference manual that says how the physical address 0x00000000 from the perspective of the general purpose M4 translates to a physical address from the perspective of the system. Revision D of the reference manual also seems to be lacking this information.

I see that the SCU can be instructed to place the image for the general purpose M4 in either the TCM of the general purpose M4, the OCRAM, or lower part of DRAM. However, from the perspective of the general purpose M4, none of these locations map to the physical address 0x00000000. How does the SCU inform the general purpose M4 to find the stack pointer and reset handler addresses at a physical address other than 0x00000000 upon PoR?

[igorpadykov]

Hi Paul

ona can look at sect.2.2.9 CM4 Memory Map, Boot Chapter i.MX8DQXP Reference Manual and

Table 5-23. Details of how SCU ROM Parses the Offset/Address in the Container Header,

sect.5.9.4.5 Image Restrictions

https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf

and SCFW documentation included in

SCFW Porting Kit

Best regards
igor
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[paul_katarzis]

Hello Igor,

Thank you for the information. Based on the documentation you cited, is the following sequence of events roughly correct?

1. The SCU ROM parses the container header for the container holding the general purpose M4 image. In particular, it parses the LoadAddr and Entry fields for the general purpose M4 image.
2. The SCU ROM loads the general purpose M4 image into the location specified by the LoadAddr field.
3. The SCU ROM passes the Entry field to the SCFW.
4. The SCFW instructs the general purpose M4 to boot at the address specified in the Entry field instead of the address 0x00000000.

If the above is roughly correct, then it is still unclear how (4) is being accomplished. Is the SCFW somehow obtaining access to VTOR in the general purpose M4 and modifying it based on the Entry field before taking the processor out of reset? I see in table 2-22 of Revision D of the reference manual that address 0x00000000 on the general purpose M4 is allocated to the "Default Slave" which is the "S_3" destination slave. What is this? Is the SCFW using this in some way to communicate the boot location to the general purpose M4?

[igorpadykov · Accepted solution]

Hi Paul

yes this understanding is correct. Unfortunately SCU details, such as

"destination slave" is not available. In general one can consider it as address remapping

so general purpose M4 sees correct start addresses.

Best regards
igor