I'm trying to implement the suggested workaround for erratum A-009885 on the T1024 platform. The document states that when MDIO_DATA returns FFFFh, the read sequence should be repeated ensuring that the time between MDIO_CTL configuration and reading MDIO_DATA is less than 80 x MDC clock period. (assuming that MDIO_CFG[PRE_DIS] is 0)
When I looked at uboot source code (file memac_phy.c , function memac_mdio_read, I noticed that after MDIO_CTL is written, it immediately starts polling MDIO_DATA, looking for MDIO_DATA_BSY to clear. MDIO_DATA_BSY (1<<31).
This BIT is not documented as valid in the T1024DPAARM (however it is referenced in other QorIQ products as valid).
I had been polling the MDIO_CFG register's busy bit before reading from MDIO_DATA. I switched my code to follow what uboot was doing and found that it functioned the same way, taking about the same time to read valid data from MDIO_DATA after writing to MDIO_CTL.
Question 1: is polling MDIO_DATA[MDIO_DATA_BSY] as uboot is doing valid?
Question 2: In the erratum workaround description, should the time between writing to MDIO_CTL and reading from MDIO_DATA measure the time between writing MDIO_CTL and the first read of MDIO_DATA (as uboot code is doing), or should it only measure the time between writing to MDIO_CTL and the first valid read from MDIO_DATA (after polling either MDIO_STAT_BSY or MDIO_DATA_BSY)?
The total time between writing to MDIO_CTL and reading valid data from MDIO_DATA seemed to take about 11.3 usecs. I calculated 80 x MDC clock period to be about 12.9 usecs (In this case FMAN frequency 500MHz, MDIO clock divisor 0x28, so MDIO clock frequency 500000000/(0x28*2 + 1) = 6172839).
In order to retry the read sequence during runtime, we would need to disable interrupts for up to 12.9 usecs which is a very long time.
However, if the answer to Question 2 is the time between writing to MDIO_CTL and doing a read from MDIO_DATA (even if not valid yet), then the time needed to have interrupts disabled would be much less.