I'm going to interface an FPGA to the i.MX RT1062 using the SEMC, operating in SYNC SRAM ADMUX 16-bit mode. I need to make sure I choose the correct pins before I make my PCB.
Why does the documentation use the term "PSRAM" in some places and "SRAM" in others? Is SRAM a subset of PSRAM? For example, in the table in "24.5.3 Pin Mux in SEMC", the "CRE" bit would only apply to PSRAM and I would not need it for the FPGA. I also wouldn't need the "Column Address bit width" bits in register SRAMCR0. All I want is the ability to burst multiple words in a single bus cycle (determined by BL bits in SRAMCR0, which ranges from 1 to 64).
I'm very confused about the chip selects. Section 24.2.2 describes memory regions, of which SRAM is Region #6. Note that Figure 23-1 is likely in error since it incorrectly shows the wrong CS signals for each type of memory. Section "24.5.3 Pin Mux in SEMC" shows "SEMC_ADDR" as being CS6, which I believe is the CE# signal shown in the timing diagrams. It is selected via IOCR.MUX_A8. Is this CE signal valid for any CS signal? For example, if both SEMC_CSX and SEMC_CSX were enabled on the A24 and A25 pins, the CE# signal would activate when either SEMC_CSX memory region was accessed? This is best described with a picture. Is this correct?
Here are screenshots of the timing diagrams that apply to my intended usage of the SEMC:
Why is cke shown in the timing diagrams? The reference manual says it only applies to SDRAM.
Is "D0", "D1", etc. Data Word 0, Data Word 1, etc.? It is confusing to use the same nomenclature as the data bits. It would be better to say something like "DW0", "DW1", etc. (assuming I'm correct in my understanding). Are 8 words shown as an example, but the range of possibilities is anywhere from 1 to 64?
Is the DQS signal required?
What is dqse?
Is ipg_clk available on a pin as well as CLK?
Thank you for your help.