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Problem with to high supply current in DeepSleep mode in LPC4370

Question asked by Robert Bąkiewicz on Jan 23, 2019
Latest reply on Jan 23, 2019 by Kerry Zhou

A schematics in the attachment shows a configuration of LPC4370 controller, where I have a trouble with too high supply current in sleep mode, which is 106uA. I use Deep Sleep mode and according to a datasheet , the current should be about 30uA. 

Would it be possible to get schematics and description of the ”preparation to get the processor to go to Deep Sleep mode” which will result in by your specification defined 30uA?    

My preparation to sleep is as follow: 

1. I turn off pullups on boot configuration lines: P1.1, P1.2, P2.8, P2.9 

2. I change the state of SPIFI CS line to high. I don't know why the bootloader leaves it in the low state and the SPIFI memory is in an active state with a high supply current . 

3. I change the main clock to internal RC 12MHz:     

reg = LPC_CGU->BASE_CLK[4];     /* Mask off fields we plan to update */    

reg &= ~((0x1F << 24) | 1 | (1 << 11));    

LPC_CGU->BASE_CLK[4] = reg | (1 << 24) | (1 << 11); 

4. I turn off PLL loops:     

LPC_CGU->PLL1_CTRL |= 1;    

LPC_CGU->PLL[0].PLL_CTRL |= 1;    

LPC_CGU->PLL[1].PLL_CTRL |= 1; 

5. I set DeepSleep mode:     

LPC_PMC->PD0_SLEEP0_HW_ENA=0x01;     /* Set Deep sleep mode bit in System Control register of M4 core */     SCB->SCR = 0x4;    

LPC_PMC->PD0_SLEEP0_MODE = (uint32_t) 0x3000aa; //Deep Sleep mode 

6. I turn off JTAG:     

LPC_CREG->CREG5=(1<<10) | (1<<11) | (1<<12);

7. The processor goes to sleep: 

__WFI();  

Attempts of boot with the use of an external SPIFI memory and by the use of JTAG interface to load and run the code, are leading to the same value of supply current. In case of JTAG interface after running the code I unplug the JTAG connector, SPIFI memory is removed in this case. Noteworthy is that turning off the JTAG in CREG5 register does not influence the supply current, the User manual UM10503 suggests that should be a difference. Hardware blocking of JTAG by setting the low state on DBGEN line (R47 in the attached schematics is removed) leads to supply current increase. It is a result of presence of an active pullup on this line inside the chip and probably it is not possible to turn it off (I did not find in manual anything how to do it).

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