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MPC8270 GPCM Burst Read/Write Timing

Question asked by Sai Krishnan J on Jan 22, 2019
Latest reply on Jan 31, 2019 by Bulat Karymov

The MPC8270 executes out of SRAM and the MPC8270 is configured to execute in GPCM mode. The MPC8270 is configured as an "Single MPC8270 bus mode" (with BCR[EBM] = 0). But the Extended transfer mode is enabled (BCR[ETM]=1). The datasheet says "Note the GPCM does not negate CS in back-to-back reads to the same device when in single MPC8280 bus mode or in 60x-compatible bus mode with extended transfers enabled."

THe data sheet also says "The GPCM provides interfacing for simpler, lower-performance memory resources and
memory-mapped devices. The GPCM has inherently lower performance because it does not support bursting."


But i do see that that burst reads/writes of 32 bytes (4 double word reads/writes on 64 bit port) are executed from time to time at least for cache reads/writes (maybe because of ETM).


The question is : Is there somewhere in the datasheet or a pdf which shows the timing diagram for the memory controller (GPCM) in this configuration (burst read/write)

I do see that the CS# remains asserted continously for 4 double word reads. I do see that the OE# or WE# gets asserted and deasserted for each of those double word reads within the 32 byte block. 

I have the CSNT bit set to provide a quarter clock cycle delay between the WE# getting deasserted to the CS# being deasserted. How does this work during a burst read/write when CS# remains asserted for 4 double words? When does the data/address change wrt to WE# within a burst cycle?


I couldnt find this in the app note AN2176