According to the i.MX RT1050 Processor Reference Manual, Rev. 2, the signal ENET_REF_CLK (on pad GPIO_B1_10) is an input in RMII mode. See Table 40-2. ENET External Signals.
Looking at the IMXRT1050-EVKB schematics, however, this signal seems to be an output from the processor, signal name ENET_TX_CLK, which is used to clock the PHY.
Can anybody please explain this apparent difference in documented signal direction.
Thanks for your help,