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The side effect/impact of SSC(Spectrum Spread) on PLL2.

Question asked by 麻生 淳一 on Jan 16, 2019
Latest reply on Jan 17, 2019 by 麻生 淳一

SSC(Spectrum Spread) is enabled and only DDR and LVDS use the PLL2 clock.

(PLL2 clock : 396MHz -> 384MHz by 23kHz step)
In the case, are there any side effect/impact to the connected devices to the clock delivered from PLL2?