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MPC5676R EBI SRAM and FLASH

Question asked by johann haller on Jan 15, 2019
Latest reply on Jan 21, 2019 by johann haller

Hello everybody,

 

I have a problem getting the EBI configured correctly.

Hardware looks like following:

CS0, 0x2000_0000 - 0x203F_FFFF FPGA

CS0, 0x2040_0000 - 0x207F_FFFF FLASH

CS1, 0x2000_0000 - 0x203F_FFFF SRAM

 

Code:

FPGA and Flash TLB 2

MAS2_VALUE(0x20000, VLE_MODE, WRITE_BACK , CACHE_INHIBIT, MEM_COHERENCE_NREQ , NOT_GUARDED, BIG_ENDIAN))

 

SRAM TLB 5

MAS2_VALUE(0x21000, VLE_MODE, WRITE_BACK, CACHEABLE, MEM_COHERENCE_REQ , NOT_GUARDED, BIG_ENDIAN))

 EBI Register see attachement EBI_REG.png

 

SIU and MMU are initialized as well.

 

Linker Command File:

/* Start address of external SRAM module */
START_EXTERNAL_RAM = 0x21000000;

 

/* Start address of external FLASH module */
START_EXTERNAL_FLASH = 0x20400000;

 

/* Start address of external FPGA module */
START_EXTERNAL_FPGA = 0x20000000;

 

Testcode after init:

START_EXTERNAL_RAM[0] = 0x11111111;
START_EXTERNAL_RAM[1] = 0x22222222;
START_EXTERNAL_RAM[2] = 0x33333333;
START_EXTERNAL_RAM[3] = 0x44444444;

 

/* Test write to FLASH */
START_EXTERNAL_FLASH[0] = 0x55555555;
START_EXTERNAL_FLASH[1] = 0x66666666;
START_EXTERNAL_FLASH[2] = 0x77777777;
START_EXTERNAL_FLASH[3] = 0x88888888;
    
/* Test write to FPGA  */
START_EXTERNAL_FPGA[0] = 0x99999999;
START_EXTERNAL_FPGA[1] = 0xAAAAAAAA;
START_EXTERNAL_FPGA[2] = 0xBBBBBBBB;
START_EXTERNAL_FPGA[3] = 0xCCCCCCCC;

 

Result in Debug: see attachment Result.png

As you can see, the SRAM is written correctly...BUT the content of the memory is persistent.

Even after a power cycle.

I monitored the CS with the Oscilloscope and BOTH CS_0 and CS_1 go low on every write, no matter what address selected.

 

Now my question: Why are both CS active? What am I doing wrong? Is there an example or at least a step by step instruction on how to use the EBI.

 

Thank you in advance for any help.

 

Johann

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