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Reset requirement for IMX7D

Question asked by Franky Hsu on Jan 15, 2019
Latest reply on Jan 16, 2019 by Yuri Muhin

Our HWPA team raised an issue that the POR_B(ResetBMCU) from PF3000 to IMX7 is deasserted before the external clock (32k/24MHz) stable. They think it is better to be deasserted after the clock source is stable but I do not find any request about this in HW design guideline.

 

Also, the reset coming from the PF3000 that I can not extend its delay time from 2mS to longer. So, if this is requirement, I do not have chance to meet it (CLK stable then reset is deasserted. )

 

Do I ignore the request from our PA team?

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