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How I can generate L1 D-Cache parity error in P2020? I am referring to e500 core document and it says: If L1CSR0[CEI] is set, any data line fill has errors injected as follows based on L1CSR0[CEIT]. Line fill operations to the L1 data cache can be created

Question asked by Arvind Srivastava on Jan 15, 2019
Latest reply on Jan 21, 2019 by alexander.yakovlev

I am trying to generate and understand handler for L1 D-Cache Parity error. After setting CEI in L1CSR0 I issued DCBF and then tried to load the same address. I got machine check. If a short code snippet to generate it can be given it will be good. Thanks