I am trying to interface K64 with SSD1963(LCD Controller) using 16-bit parallel(8080-mode) Flexbus at 48Mhz.
Data lines and Chip Select line of flexbus are working fine but other control lines(Data/Command,Write) are not working properly.
Please help me to configure the flexbus for SSD1963.
Please find attached image of waveform for reference.
Init function of Flexbus
void Init_FLEXBUS_LCD_port_GPIO(void) //Init flexbus interface
{
SIM_SCGC5 = (0 | SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK| SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK) ; //Enable clock PORTA,PORTB,PORTC,PORTD & PORTE for LCD interfacing
/* Configure the pins needed to FlexBus Function (Alt 5) */
PORTB_PCR18=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB15
PORTC_PCR0=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB14
PORTC_PCR1=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB13
PORTC_PCR2=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB12
PORTC_PCR3=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //PORT_PCR_MUX(1)->PORT_PCR_MUX(5)//LCD_BLE
PORTC_PCR4=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB11
PORTC_PCR5=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB10
PORTC_PCR6=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB9
PORTC_PCR7=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB8
PORTC_PCR8=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB7
PORTC_PCR9=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB6
PORTC_PCR10=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB5
PORTC_PCR11=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //LCD WR & RD
PORTC_PCR12=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //PORT_PCR_MUX(1)->PORT_PCR_MUX(5)//RESET
PORTC_PCR13=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //PORT_PCR_MUX(1)->PORT_PCR_MUX(5)//LCD C/D
PORTC_PCR14=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //PORT_PCR_MUX(1)->PORT_PCR_MUX(5)//LCD DISP_ON
PORTC_PCR15=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //LCD_23
PORTD_PCR1=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //LCD_CS
PORTD_PCR2=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB4
PORTD_PCR3=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB3
PORTD_PCR4=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB2
PORTD_PCR5=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB1
PORTD_PCR6=(0|PORT_PCR_MUX(5)|PORT_PCR_DSE_MASK); //DB0
SIM_SOPT2 |= SIM_SOPT2_FBSL(3); // Security access off
SIM_SCGC7 |= SIM_SCGC7_FLEXBUS_MASK; // Flexbus clock enable
FB_CSAR0 = FLEX_DC_ADDRESS; //CS0 Base address
FB_CSMR0 = FLEX_ADRESS_MASK | FB_CSMR_V_MASK;
FB_CSCR0 = FB_CSCR_PS(2) // 16-bit port
| FB_CSCR_AA_MASK // auto-acknowledge
| FB_CSCR_ASET(0x2) // assert chip select on second clock edge after address is asserted
// | FB_CSCR_WS(0x1) // 1 wait state - may need a wait state depending on the bus speed
| FB_CSCR_BLS_MASK // RMB Byte lane shift enable
;
}
#define FLEX_DC_ADDRESS 0x60000000
#define FLEX_ADRESS_MASK 0x00010000//0x00010000
#define FLEX_DATA_ADDRESS 0x60010000
Write Data function
void Write_Data_16BIT(unsigned long data1)
{
unsigned short Data_BUS=0;//,Temp=0;
if(LCD_FLEX_BUS_MODE)
{
*(unsigned short*)(FLEX_DATA_ADDRESS) = data1; //write
}
}
Write Command function
void Write_Command(unsigned char command)
{
if(LCD_FLEX_BUS_MODE)
{
*(unsigned short*)(FLEX_DC_ADDRESS) = command;
}
}
