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LS1012ARDB - PCIe IO Coherency

Question asked by Bas Vermeulen on Jan 10, 2019
Latest reply on Nov 6, 2019 by Jefferry Zhu

First some context:
I am connecting an AMD Radeon GPU to the LS1012ARDB's mini PCIe slot in order to get it working with linux.

The GPU is visible on the PCIe bus, enumerates, gets it's BAR's assigned, and is recognized by the driver.

However, when it tries to get the GPU to write to a specific memory location, it fails.


Reading the reference manual (LS1012ARM.pdf, page 1237, section 25.1) it says the following:


The PCI Express controller as instantiated on this chip does not support hardware coherency. All incoming PCI Express transactions are made non IO-coherent.


Does this mean that when a PCIe device writes something into main memory, the caches aren't updated? If not, what does it mean? ARM - Cache coherency fundamentals seems to imply this.




Bas Vermeulen