We reset the receiver time-out interrupt with a RX FIFO reset (write access to FCR with value 1). This works fine for quite a while, but there is a chance to end up with a receiver time-out interrupt staying in pending mode. The /IRQ signals stays low. The interrupt source is verified with a read access to IIR register returning 0xCC. We considered the timing and respect the 2 x Tclk of XTAL1 requirement from datasheet. We use a external oscillator with 48MHz and 3.3V power supply. A new character received on UART RX creates a reset of the interrupt so does the read access to RHR.
Does anybody have another idea why the interrupt stays pending while reseting the RX FIFO?
Is there any application note available about reset methods of each interrupt source similar to the description in 16C450 datasheet?