i.MX6 VDDARM_IN voltage during reset

[sugiyamatoshihi]

Hi,

I have a question about voltage of VDDARM_IN and VDDSOC_IN during Reset.

VDDARM_IN and VDDSOC_IN are connected together and voltage applied at 1.42V, However, when VDDARM_CAP and VDDSOC_CAP turn on, 1.42V drop to 1.17 in short time during reset.

I think it is no problem because it is during reset and voltage is more than sleep mode voltage 0.9V.

Can you think of something to be a problem?

Best Regards,

Sugiyama

[sugiyamatoshihi]

Hi, Yuri,

Thanks for your comment.

Best Regards,

Sugiyama

[Yuri]

Hello,

  The i.MX6  VDDARM_IN and VDDSOC_IN voltages should not violate corresponding specs in

Operating Ranges tables of i.MX6 Datasheet(s).  Also, let me remind, according to Table 2-6 (Power

and decouple recommendations) of Hardware Development Guide for i.MX6:

 VDD_SOC_IN requires a 66 uF bulk capacitance.

Have a great day,

Yuri

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[sugiyamatoshihi]

HI, Yuri,

Thank you for answer.

Customer already use 66uF for VDD_SOC_IN. 

I think  voltage of these power line during reset could corresponding to Stand by voltage.

Do you agree this?

Best Regards,

Sugiyama

[Yuri]

Generally - yes.