on a custom board I see that VDD_PU cap is cycling on and off and wonder if that behavior is expected?
Running Linux 4.9.11.ga.
It cycles in periods of 1 to 1.5s when running a QT app with eglfs. When not running the app it stays off (~0.20V)
Looking at the PMU_REG_CORE with devregs the VDD_PU bit-field (REG1_TARG) toggles as well, between 00 and 26 (1175mV), e.g.
Using internal LDOs, no PMIC. SOC_IN supplied by 1.38V fixed regulator.
Is this behavior expected, and is it managed like this?