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i.mx6Solo VDD_PU_CAP cycling on / off

Question asked by ThomasG1z on Jan 9, 2019
Latest reply on Jan 9, 2019 by igorpadykov



on a custom board I see that VDD_PU cap is cycling on and off and wonder if that behavior is expected?

Running Linux


It cycles in periods of 1 to 1.5s when running a QT app with eglfs. When not running the app it stays off (~0.20V)


Looking at the PMU_REG_CORE with devregs the VDD_PU bit-field (REG1_TARG) toggles as well, between 00 and 26 (1175mV), e.g.

0x020c8140     =0x004c0012

0x020c8140     =0x004c2612


Using internal LDOs, no PMIC. SOC_IN supplied by 1.38V fixed regulator.


Is this behavior expected, and is it managed like this?