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How long is it valid for FLL lock?

Question asked by sarah wang on Jan 9, 2019

Hi All,

I am having problem when I use a demo routine to set FEE mode for S9KEAZ128.

The bold line is to wait for FLL to lock, and it takes about 26ms, I think it is too long for initialization.

How long is it valid for FLL lock?

 

20.5.3 Initializing FEE mode

The following code segment demonstrates setting ICS to FEE mode.
Example: 20.5.3.1   FEE mode initialization routine
/* the following code segment demonstrates setting the ICS to FEE mode generating a 40MHZ core clock frequency using an external 8MHz crystal */

OSC_CR = 0x96; // high-range, high-gain oscillator selected

while ((OSC_CR & OSC_CR_OSCINIT_MASK) == 0); // wait until oscillator is ready

ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configured

ICS_C1 = 0x18; // 8MHz external reference clock/256 as source to FLL

while ((ICS_S & ICS_S_IREFST_MASK) == 1); // wait for external source selected

while ((ICS_S & ICS_S_LOCK_MASK) == 0); // wait for FLL to lock

SIM_CLKDIV = 0x01100000; // core clock = ICSOUT/1 and bus clock = core clock/2

ICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies

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