AnsweredAssumed Answered

UART2 issues when recovering from VLPS on the K50 Processor

Question asked by Thasin Akhand on Jan 8, 2019
Latest reply on Jan 10, 2019 by Thasin Akhand

Hi,

 

I see framing issue when I send a serial message via UART2 on RS485 line with 9600 baud rate with data size of 8-bit, and no parity. This issue happens when I had implemented VLPS. When the VLPS wakes up from uart rising edge, I do set the processor back to PEE (with PLL locking), however I am still not receiving any messages. I read in some forums to use external clock for your uart, but what if you don't have an external clock and the reference manual says the UART2 is operated by the bus clock only? The bus clock is affected by entering the VLPS, so my question is, is there any other solution or am I missing something? Run to VLPS currently switches in freeRTOS idle hook. 

 

I am using #MK50DX256CMC10 kinetics processor. 

 

Thank you. 


Regards,
Thasin

Outcomes