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LS1043A CSn bus timing issue

Question asked by Gary Beck on Jan 7, 2019
Latest reply on Jan 8, 2019 by Gary Beck

We have a custom LS1043A board with the following peripherals mapped


CS0 - NOR Flash (256MB)

CS1 - NOR Flash (256MB)

CS2 - 8 bit GPCM (64KB)

CS3 - 16 bit GPCM (64KB)


Seeing some strange bus timing on CS2 and CS3 when CS0 write cycles are heavily utilized.  Seems as though the write cycle timing from the CS0 region is being applied to the write cycles for the CS2&3 regions for a short period of time.  The bus timing does revert back to the programmed values once the CS0 accesses cease.  The bus timing for CS0 is the same as the RDB.  The bus timing for CS2&3 are much longer (x10) due to design constraints.  


Has anyone seen varying bus timing on the LS1043A IFC interface?  Is there any errata?