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BSC9132 custome board ddr3 validation

Question asked by manju patil on Jan 7, 2019
Latest reply on Feb 18, 2019 by manju patil

Hello team NXP,

We built the custom BSC9132 board but not changed the ddr3 chips that is used in the bsc9132qds board. Only layer stack changed because of this execution of  BSC9132QDS_init_core stops infinitely with log

cmdwin::wait 50
cmdwin::eclipse::config runcontrolsync on
cmdwin::stop
ccs_stop_core
coreh = [serverh:0;cc_index:0;chain_pos:1]
ccs_stop_core; ccs_error = -2147418099
Error message: ELF is not in expected HALT mode

 

then i thought we should run the ddr validation on this but non of the test are getting passed on the board.

each test failed with the following error.

 

DDR enable error: timeout occurred while waiting for SDRAM_CFG_2[D_INIT]

 

ddr validation project set up is working(i.e validation happens and gives good configurations) on the bsc9132qds(evaluation board) since our board has same ddr chips i am using the same project for our board also. 

Please someone help me to resolve this problem

 

Regards

Patil

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