AnsweredAssumed Answered

MMU TLB table difference for T4160 Target

Question asked by vinothkumar s on Jan 5, 2019
Latest reply on Jan 5, 2019 by alexander.yakovlev

Hi All,


I am working on T4160RDB board to do MMU setup. I confused with MMU TLB table configuration.


Which one is correct according the DDR and NOR Flash?



init_rev.cmm from Lauterbach Trace32 Script,

;MMU Setup
;NOR FLASH 0xe8000000--0xefffffff (1GB)
MMU.TLB1.Set 0. 0xC0000A00 0xe8000008 0xe8000015 0x00000000 0x00000000
;DDR 0x00000000--0x3fffffff (1GB) 
MMU.TLB1.Set 1. 0xC0000A00 0x00000000 0x00000015 0x00000000 0x00000000



T4240RDB_init_core.tcl from CodeWarrior Flashprogrammer,

# define 256M TLB entry 4 : 0xE0000000 - 0xEFFFFFFF for NOR cache-inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM4 = 0x9000000A1C08000000000000E000000000000000E0000001


# define MAX_DDR TLB entry 2 : 0x00000000 - 0x7FFFFFFF for DDR cacheable, M
reg ${CAM_GROUP}L2MMU_CAM2 = 0x${DDR_TLB_SIZE}0000041C08000000000000000000000000000000000001



Which one I want to take for Lauterbach Trace32 Script and What could be the issue?




Thanks & Regards,