I have a query on the Platform clock setting in our T4160 board.
, I am setting SYS_PLL_RAT using the [2:6] bits of RCW. One observation i made is whatever ratio I use in RCW, SYS_PLL_RAT is always 6:1. This i have confirmed by reading the CFG field of PLLPGSR register. Similary whatever ratio of MEM_PLL_RAT, I set using RCW, MEM_PLL_RAT is always 10:1 only. This is confirmed by reading PLLDGSR register.
What could be the reason for that?