I am using a flexio to manage communication with ADS1222 24 bit Analog to digital converter.
One shifter for the serial data got on the DRDY/DOUT signal.
One timer generating shift clock and the SCLK clock signal
The trigger of the timer should be the falling edge of the DRDY/DOUT signal.
What's happening during timer decrementing if there are falling edges on the DRDY/DOUT signal ?