I'm hoping someone up out there is familiar with the boot up flow of the Vybrid processor. I have an OTS SOM that will be booting the A5 core from QSPI flash (located on the SOM) in DDR x2 mode, with the code ending up in DDR memory. I’m trying to fill in the data structures and understand the boot flow. I understand the QuadSPI Configuration Parameter block Table 7-21 and the basics of the IVT.
My understanding of the first part of the boot flow with QSPI is:
- -The QSPI clock is configured to run at 18 MHz. What speed is the processor clock?
- -The QSPI pins are configured.
- -Do basic QSPI read operation starting at flash location 0 (318 bytes) to get configuration parameters
- -Re-configure the QSPI controller per the parameters
- -Re-configure the clock to run the QSPI controller at 66 MHz (from parameter). What does this do to the processor clock?
I assume that the following (or something like it) is what happens next:
- -The boot loader reads the first 4KB(??) from flash starting at location 0 into OCRAM memory starting at 0x3f00_0000(??). It then knows that the IVT will be at 0x3f00_0400.
- -Executes any instructions in the DCD (set processor clock to 396 MHz and enable the DDR cntlr).
- -Using the info in the BOOT data struct Table 7-54 (start and length), “length” bytes (the code image) are loaded into memory starting at location “start”. How does the boot loader know where the image is in flash memory?
- -Boot loader “jumps” to the entry point “entry” given in the IVT.
How much of the above is actually correct?
When the QSPI clock is at 66 MHz, what speed is the A5 core running at? (I assume 396 MHz)
What location is the “boot stuff” copied into in OCRAM? If it is 0x3f00_0000, what happens when the app code is also loaded into the same space? How many bytes are read in?
How does the boot loader know where the app code is in flash memory?
Can the QSPI controller function properly in DDR mode during boot? I haven’t seen any of the examples use it. They all use SDR mode.