i.MX8M DDR calibration failure in u-boot-2018.03-4.14.78-ga

[felixradensky]

Hello,

We're using RPA Tool V18 and DDR Tool V1.1 from i.MX8MSCALE DDR Tool Release  to generate LPDDR4 init code in ARRAY format for u-boot-2018.03-4.14.78-ga. Our board is based on i.MX8M B0 silicon. Inside DDR Tool both calibration and DDR test pass successfully. However when generated lpddr4_timing.c in integrated into u-boot, DDR init fails with the following errors:

U-Boot SPL 2018.03-00924-g654088c-dirty (Dec 24 2018 - 17:42:33 +0200)

PMIC:  PFUZE100 ID=0x10

DDRINFO: start lpddr4 ddr init

DRAM PHY training for 3200MTS

check ddr4_pmu_train_imem code

check ddr4_pmu_train_imem code pass

check ddr4_pmu_train_dmem code

check ddr4_pmu_train_dmem code pass

Training PASS

DRAM PHY training for 668MTS

check ddr4_pmu_train_imem code

check ddr4_pmu_train_imem code pass

check ddr4_pmu_train_dmem code

check ddr4_pmu_train_dmem code pass

Training FAILED

DRAM PHY training for 3200MTS

check ddr4_pmu_train_imem code

check ddr4_pmu_train_imem code pass

check ddr4_pmu_train_dmem code

check ddr4_pmu_train_dmem code pass

Training PASS

DDRINFO:ddrphy calibration done

DDRINFO: ddrmix config done

Normal Boot

Trying to boot from MMC2

"Synchronous Abort" handler, esr 0x96000000

elr: 00000000007ea160 lr : 00000000007eab18

x0 : 0000000042200080 x1 : 0000000042200010

x2 : 0002000000022f68 x3 : 00000000422000a8

x4 : 0000000000000000 x5 : 0000000000000000

x6 : 0000000000000005 x7 : 00000000422000b0

x8 : 0000000000000001 x9 : 0000000000000001

x10: 0000000000000002 x11: 000000000000000b

x12: 000000000000001f x13: 000000006d72a038

x14: 0000000000901590 x15: 00000000ffffffff

x16: 000000000a9ee9bd x17: 0000000058f4f155

x18: 0000000000185e40 x19: 0000000042200080

x20: 0000000042200010 x21: 0000000030b40000

x22: 00000000000001a8 x23: 0000000000000000

x24: 00000000007f3477 x25: 00000000007f9000

x26: 00000000deadbeef x27: 0000000000000000

x28: 0000000000000000 x29: 0000000000185c90

Resetting CPU ...

If instead of generating ARRAY format sources we generate CODE format sources (ddr_init.c and ddrphy_train.c) and use them instead of DDR driver (drivers/ddr/imx8m) and lpddr4_timing.c, u-boot successfully configures the DDR and boots Linux. We suspect that there's a problem with DDR driver and/or ARRAY format code. We would really like to use ARRAY code and the driver, to avoid code duplication between B0 and B1 DDR init code.

Attached please find DDR init script, source files generated by DDR Tool and DDR Tool Log.

Your help in resoling this problem will be much appreciated.

Felix.

[felixradensky]

Hi,

The problem is fixed in latest DDR Tool release, V.1.11. Previous version was generating code for 668MHz frequency, while u-boot DDR driver was expecting to find 667MHz in the generated code. As a result DDR training failed.

Felix.