I want to get more details about the Decorated memory storage controller in S32R274 controller. What are the chip specific decoration values and its effect on the memory? Please provide the supporting documents for the same.
Expecting a reply from NXP for DMSC. Please support. Thanks
It is hardware support for atomic read-modify-write memory operations in the Power Architecture, these capabilities are called "decorated storage". It is supported by capabilities in the processor cores plus instantiations of a DecoratedStorage Memory Controller (DSMC).The Decorated Storage APU defines instructions for providing load and store operations to memory addresses that require additional semantics beyond just the reading and writing of data values to the addressed memory locations. Decorated storage operations are intended to be used for specific devices or memory targets that require these additional semantics. A "decoration" is the additional semantic information to be applied to the decorated storage operation by the DSMC.
I am aware about the read-modify-write capability of decorated storage controller. I specifically need the information on semantics associated with the decorated load and store instructions for the S32R274 controller.
For example: I need to load a word from memory with a particular bit set in "atomic" way, what is the decoration value to be supplied to lwdx instruction?
Any application note on this topic will be much helpful. Thanks.
Retrieving data ...