we have interfaced SDRAM (IS42S86400F-7TLI) with processor MPC8270. Following is the issue that we are facing running SDRAM with MPC8270.
If we write 0x12345678 at SDRAM address 0x00000000. The data is correctly written at address 0x00000000. But when we read from 0x2000 same data that we wrote (i.e. 0x12345678) at 0x00000000 will be read from this location. It seems like the 11th bit of column address is not working. When we change the driver to used 10 columns address lines, the data repetition problem is resolved.
(1) Kindly tell us how to configure SDRAM with 11 columns in SDRAM machine configuration registers?
(2) Does MPC8270 support SDRAM with 11 columns (A [0-9, 11])? If yes, what should be the proper changes in hardware or software? Should the multiplexing be configured in software or do we have to do external multiplexing?
(3) A similar problem is mentioned in AN2165 (Page 3) “Column Number Limitation for MPC8260 Rev. A and B”. Does the same problem resides in MPC8270 as well? If Yes, how do we resolve this problem (i.e. using an SDRAM with 11 columns (A [0-9, 11]))?
Following are the software and hardware configurations for our board:
(1) 100 MHz Bus frequency
(2) 400 MHz Core frequency
(3) 300 MHz CPM frequency
(4) 512MB SDRAM (8 devices, each 64MB of x8 width arranged in 16M x 8 bits x 4 banks, all connected via CS1)
SDRAM (IS42S86400F-7TLI) Specifications:
(1) 16M x 8 bits x 4 banks
Note: 8 devices(x8) are interfaced to MPC8270 using 64-bit data bus
(2) 13 Rows (A0 – A12), 11 Columns (A0 – A9, A11)
(1) PSRT: 0x0200
(2) MPTPR: 0xF9 Note: Refresh interval will be 7.5uSec
Interval = (249+1) x (2+1)/100000000 = 7.5uSec //8192 rows having 64ms refresh time yields 7.8uSec
(3) OR0: 0xE0002700
SDAM = 0b111100000000
LSDAM = 0b00000
(4) BR0: 0x00000041
(5) PSDMR: 0xC536B673