In several places I've read that the trace clock frequency is usually half that of the core clock frequency. One such place is the following link: https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/
"The trace clock speed (TRACECLK) is on most microcontrollers directly dependent on the CPU clock speed and is usually half of the CPU clock speed". In the i.MX RT 1060 data sheet, the maximum trace clock frequency is listed as "ARM_TRACE_CLK frequency of operation", and has a max value of 70 MHz. This is substantially less than 1/2 the max core frequency of 600 MHz, which would be 300 MHz. It appears the trace bus is 4 bits wide. Is the width the reason the trace clock can be 70 MHz? Even at 4 * 70 MHz = 280 MHz, that is still less than half the max clock frequency of 600 MHz. Is the amount of trace information limited in order to run at such a low trace clock frequency? Or is all of the potential information present and it is right on the edge of the bandwidth limit?