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Why the I2S MCLK output frequency of KL26 is not correct?

Question asked by Max pi on Dec 18, 2018
Latest reply on Dec 24, 2018 by Max pi

Dear,

In my design, the MCLK is mapped to PTC4. The epected frequency of MCLK is 12.288MHz, divided from PLL_CLK 48MHz.

But when configured, the output frequency of MCLK on PTC4 pin, is always 48MHz, although the MDR regisiter is set to deifferent values, it seems that the MDR value doesn't work.

The clock configure code is as follow. Please help check why the MCLK is not 12.288MHz.

 

    CLOCK_EnableClock( kCLOCK_Sai0 );

 

    //master clock source: PLL_CLK, MCR[MICS] = 11b
    I2S0->MCR |= I2S_MCR_MICS(3);

 

    //Enable MCLK output, MCR[MOE] = 1b
    I2S0->MCR |= I2S_MCR_MOE(1);
    
    //Set the FRACT and DIVIDE. MCLK = master clock/(FRACT+1)/(DIVIDE+1), FRACT = 255, DIVIDE = 999
    I2S0->MCR &= ~I2S_MCR_DUF_MASK;
    I2S0->MDR =( I2S_MDR_DIVIDE(1000 - 1)  |  I2S_MDR_FRACT(256 - 1) );

 

    while( I2S0->MCR & I2S_MCR_DUF_MASK ){                // check MCR[DUF]
    }
   
    //TCR2[MSEL](27-26) = 01b, TCR2[BCD](24) = 1b, DIV(7-0) = 4/2-1 = 1
    I2S0->TCR2 |= (0x00000001<<26) | (0x00000001<<24) | (0x00000001);
    
    //Rx clock set, internally generated, Rx BCLK = MCLK/4, 12.288M = 3.072*4 = 48K*32*2
    I2S0->RCR2 |= (0x00000001<<26) | (0x00000001<<24) | (0x00000001);

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