AnsweredAssumed Answered

MIPI_DSI timing setting

Question asked by jan mennen on Dec 14, 2018
Latest reply on Dec 21, 2018 by jan mennen

Hello

I have difficulty in finding the write settings to drive a panel with resolution 1344x1760. This panel is connected via TI MIPI to LVDS bridge.

 
After a lot of trail and error i find a timing which gives valid output. Clock frequency is however only 80 MHz
When increasing the clock to 100 MHz i get still valid hsync pulses but no vsync. Because i still get the hsync i assume it is not a timing problem

 

I see also that when i increase the vertical frontporch to 20 i don't get any valid MIPI signal anymore.

 

Question is how can i define the correct setting for a given resolution and are there restrictions in vertical and horizontal blanking setting?

 

This is current setting. The target is to drive with higher clock up to 145 MHz to get 60 Hz frame rate

 

static const struct drm_display_mode cid_cid1344_mode = {
.clock = 80000,
.hdisplay = 1344,
.hsync_start = 1344 + 20,
.hsync_end = 1344 + 20 + 40,
.htotal = 1344 + 20 + 40 + 120,
.vdisplay = 1760,
.vsync_start = 1760 + 2,
.vsync_end = 1760 + 2 + 4,
.vtotal = 1760 + 2 + 4 + 2,
.vrefresh = 30,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
};

 

Thanks Jan

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