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T1042 DDR Controller Output Clock Issue

Question asked by Ather Shehzad on Dec 13, 2018
Latest reply on Dec 14, 2018 by Bulat Karymov

Hello all!
I have designed a custom board using T1042 processor and I have interfaced 8GB RAM using two ranks. The configuration of the RAM is 8Gb x16 per chip. Each rank have 4 separate chips + 1 extra chip for ECC. So in total I have 10 discrete DDR3L Chips (AS4C512M16D3L-12BIN). 5 chips are interfaced through CS0 and 5 chips are interfaced with CS1. 

Currently I am using CodeWarrior DDRv tool to validate my RAMs. When I run centering the clock test it gives out error "D_INIT was not cleared by Hardware". To check the working of DDR controller and discrete RAMs chips we reduced the operating speed of the RAM to 600 MHz and also now we are using in it 32-bit mode and only CS0 is enabled. Still we are getting the same error.

While debugging we checked our DDR Clock on oscilloscope because as a first step we can doubt our clocks. Can anyone please verify whether my DDR_MCLK0 is fine or not ?