I have a custom board with sys_clk = 66.66 MHz, ddr_clk=66.6MHz.
And Hard coded RCW is used for board bring up as we dont have programmed flash yet.
Through scope we have seen that the T2081 has come out of Reset power on sequence.
1. But i still get in PLL status registers "PLL disabled"
2. No output at "clk_out" even when configured proper clock domain control status register is programmed?
3. I am able to alter the register contents, toggled GPIO, able to program CPC RAM, Transmitted data on UART then why it shows PLL disabled?