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Vybrid : Setting core supply when executing SW RESET

Question asked by Eishi Shibusawa on Dec 12, 2018
Latest reply on Jan 4, 2019 by Edward Karpicz

Dear Sir

 

I would like to ask about the STEPs for the SW Reset.

 

I refer to the following community and AN4807 Rev.0, 10/2013.

https://community.nxp.com/message/522684?q=Vybrid%20SW_RST

Customers refer to AN 4807 Figure 6.

It is described as the follows in the community.

This switchover circuit is a make-before-break circuit with ~1ms of crossover time controlled by a single Vybrid GPIO which defaults to the Vybrid's internal LDO.

SW Reset without Switching supplies beforehand: 0x00001201 (unexpected)

SW Reset after Switching to the Vybrid's LDO: 0x00040000 (expected)

 

Q1.

How should the core supply be set before issuing SW RESET?

(What is the Vybrid's LDO?)

(LDO with external ballast transistor? or internal LDO??)

 

It is described as the follows in the AN4807 P16.

Low power stop mode sequence:

1. Stop extensive part of the code.

2. Switch to power from external ballast transistor using GPIO pin.

 a) Open right FET transistor to start feeding from external ballast transistor.

 b) Close left FET transistor to stop supplying from 1.2 DC/DC converter.

 c) Disable DC/DC.

3. LDO with external ballast transistor is used.

4. Jump in to low power stop mode.

5. Core is powered from internal LDO.

 

Executing STEP 2 a-c above, the core power supply will be changed to LDO with external ballast transistor.

Q2.

If it is necessary to change the power supply to the internal LDO before executing the SW RESET, should we execute STEP 4?

 

Best Regards,

Eishi SHIBUSAWA

 

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