Hi,
I am looking for timing requirements for power-on reset, i.e. the minimum time between VDD up and !RESET gets HIGH.
The datasheet contains a diagram (see attached), but without timing information.
Thanks,
Martin
FAE EBV
Hi, there is even application note dealing with this timing in the great detail. Pay attention to the link below:
https://www.nxp.com/files-static/microcontrollers/doc/app_note/AN4768.pdf
Great, thanks David!
never-displayed